Recently, a SRAM adopts a pre-charge circuit, which raises a potential of a write/read bus to a predetermined level in advance of data-reading in order to improve the speed of data-reading. Thereafter, a conventional data out buffer circuit of the SRAM provided with the pre-charge circuit will be explained.
A conventional data out buffer circuit is composed of a write/read bus which transmits an output signal of a sense amplifier, the above-mentioned pre-charge circuit, and a data output circuit which is supplied with a data transmitted from the sense amplifier via the write/read bus. In a period of data-reading, the pre-charge circuit is inoperative, and the data supplied from the sense amplifier is transmitted directly to the data output circuit. However, during the period of pre-charge, since the potential of the write/read bus is maintained at a predetermined level, it becomes impossible to hold the data read before then on the write/read bus. That is to say, the conventional data out buffer is defective in an output data holding-characteristic, and further improvement is extremely desirable.